1. Field of the Invention
This invention relates to a process for shallow trench isolation (STI) in a semiconductor structure, more specifically, to a method for improving the STI step uniformity.
2. Description of the Prior Art
In the manufacturing process for semiconductor integrated circuits such as DRAMs, shallow trench isolations (STI) are often used to isolate the respective elements.
Generally, in the semiconductor device such as a DRAM, a pad oxide layer with a thickness of about tens angstrom is deposited on a substrate, and then a pad nitride layer, of which the material can be SiN, with a thickness of about a thousand angstrom above is deposited on the pad oxide layer. The intermediate structure having the substrate, the pad oxide layer and the pad nitride layer is subject to steps of photo-mask developing, etching and removing the mask and the like to form shallow trench isolations. The formation of STIs separate active regions of the semiconductor structure.
With reference to FIG. 1, a structure in shown with STIs 20 and 21 formed. In this drawing, the reference numbers 10 and 11 indicate substrate, 12 and 13 indicate pad oxide layers, 14 and 15 indicate pad nitride layers. As shown, in the whole semiconductor device structure, a phenomenon that the STIs 20 and 21 in different regions have different depths is likely to happen.
With reference to FIG. 2, under the situation that the depths of STIs 20 and 21 are not uniform, when using high density plasma (HDP), for example, to form an oxide layer 30 on the whole structure, the overfill thickness t of the oxide at the region of the shallow STI 20 will be thicker than that at the region of the deep STI 21.
Then, the oxide layer 30 is planarized by chemical mechanical polishing (CMP). The height difference between the top of the planarized oxide layer 30 and the top of the substrate of the active region is referred to STI step. As can be seen from FIG. 3, since the overfill thicknesses of the oxide are different, after planarization, the STI steps in the regions of STIs of different depths are different. As shown in the right part of FIG. 3, it is possible that the nitride layer 15 is partially removed in the polishing step.
In the process for DRAM, the active regions separated from each other by the STIs will have gates or bit lines formed thereon. Generally, in DRAM structure, the non-uniformity of the STI steps is likely to cause gate stringer, thereby causing improper short circuit between the gates or between the gate and bit line.
Therefore, a solution to solve the above problems is necessary. The present invention satisfies such a need.